signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 the spt5220 is a monolithic 10-bit, 80 mwps cmos d/a converter for high-resolution color graphics and video system applications. the device operates from a single +5 v power supply and all digital inputs are ttl/cmos compatible. the spt5220 generates rs343a-compatible video outputs (capable of driving a doubly-terminated 75 w load) and spt5220 10-bit, 80 mwps video dac general description applications ? high resolution color graphics ? medical electronics: cat, pet, mr imaging displays ? cad/cae workstations ? general purpose high-speed d/a conversion ? direct digital synthesis (dds) ? digital radio transmitters/modulators ? high definition television (hdtv) features ? 80 mwps pipelined operation ? +5 v cmos monolithic construction ? 0.4 lsb differential linearity error ? 0.6 lsb integral linearity error ? ttl-compatible inputs ? rs-343a/rs-170 compatible outputs ? binary or two's complement input data format ? low power dissipation of 260 mw ? internal/external voltage reference rs170-compatible video outputs (capable of driving a singly- terminated 75 w load) without the need for external buffers. the data latches minimize the data time skew and reduce the glitches that can adversely affect many applications. the device is available in a 28-lead plastic dip package over the commercial temperature range. block diagram a a 3 10 digital input buffer first latch 5 31 5 3 36 3 second latch dac i out comp r set v ref amp dv dd dv ss v bb av dd av ss bgr clock generator code d -d9 n2c inverse clock decoder sync blank bright cm
spt 2 12/30/98 spt5220 electrical specifications 4 t a =t min to t max , av dd =dv dd =v bb =+5.0 v, av ss =dv ss =0.0 v, v ref =1.235 v, r set =165 w , unless otherwise specified. test test spt5220 parameters conditions level min typ max units dc characteristics resolution 10 bits differential linearity error vi 0.4 1.0 lsb integral linearity error vi 0.6 1.0 lsb gray scale error vi 5.0 % gray monotonicity vi guaranteed digital input high current v in =2.4 v vi 1.0 m a digital input low current v in =0.4 v vi -1.0 m a digitial input capacitance f in =1 mhz iv 20 40 pf analog outputs gray scale current vi 22 ma output current bright to white vi 1.0 1.90 3.0 ma white to black vi 18.1 19.05 20.0 ma black to blank vi 0.5 1.43 2.5 ma blank to sync vi 6.5 7.62 8.5 ma sync level vi 0 5 50 m a lsb size v 18.62 m a output compliance vi -1.0 +1.5 v output impedence v 11 k w output capacitance f in =1 mhz iv 14 30 pf internal reference voltage vi 1.16 1.235 1.36 v power supply rejection ratio f in =1 khz, comp=0.1 m f v -30 db operating supply voltage vi 4.75 5.00 5.25 v digital input voltage high vi 2.0 v dd +0.3 v low vi v ss -0.3 0.8 v effective output load v 37.5 w data input setup time iv 2.0 ns data input hold time iv 2.0 ns clock cycle time iv 12.5 ns clock pulse width high iv 5 ns clock pulse width low iv 5 ns absolute maximum ratings (beyond which damage may occur) 1,2,3 esd susceptibility .............................................. 2,000 v temperature operating temperature range (ambient) ..... 0 to +70 c storage temperature ................................ -55 to +150 c notes: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. 2. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. 3. applied voltage must be current limited to the specified range. supply voltages av dd .......................................................... -0.5 to +7.0 v dv dd ......................................................... -0.5 to +7.0 v input voltages any digital pin .................... dv ss -3.0 v to dv dd +3.0 v note: 4. to avoid power latch-up, drive all supply pins (av dd , dv dd , and v bb ) from the same source.
spt 3 12/30/98 spt5220 electrical specifications t a =t min to t max , av dd =dv dd =v bb =+5.0 v, av ss =dv ss =0.0 v, v ref =1.235 v, r set =165 w , unless otherwise specified. test test spt5220 parameters conditions level min typ max units ac characteristics clock rate 80 mwps analog output delay v 7 ns analog output rise time v 4 ns analog output fall time v 4 ns analog output settling time 5 to 1 lsb iv 100 150 ns to 2 lsb iv 70 100 ns clock and data feedthrough 5 v -34 db glitch impulse 5 iv 30 pv-sec differential gain error v 0.8 % differential phase error v 0.9 degree pipeline delay (clock latency) iv 1 clock cycles v dd supply current 6 vi 50 70 ma test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. test procedure 100% production tested at the specified temperature. 100% production tested at t a =+25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range. test level i ii iii iv v vi note: 5. clock and data feedthrough are functions of the amount of overshoot and undershoot on the digital inputs. for this test, the digital inputs have a 1 k w resistor to ground driven by 74hc logic. settling time does not include clock and data feedthrough. glitch impulse includes clock and data feedthrough. 6. at f max , idd (typ) at av dd =dv dd =5.25 v, clk=0 v to 3 v (80 mwps), nc2=high, data (d?-d9)=0 v to 3 v (40 mwps), inverse=sync=blank=bright=low.
spt 4 12/30/98 spt5220 table i - video output truth table sync blank bright data (d9-d0) i out (ma) v out (v) out (ire) description 1 x x x 0 0 -40 sync level 0 1 x x 7.62 0.286 0 blank level 0 0 0 000 9.05 0.340 7.5 black level 0 0 0 111 28.10 1.054 100 white level 0 0 1 000 10.95 0.410 17.5 enhanced black level 0 0 1 111 30.00 1.125 110 enhanced white level circuit description and operation the spt5220 contains a 10-bit dac, input buffers and latches, internally or externally generated voltage refer- ence and complete video controls. the following describes the main operation of the device and outlines several considerations that should be noted to achieve the best performance. clock input clk is the device clock input and is typically the pixel clock rate of the system. it is ttl compatible. the digital data d0-d9 and all video controls (sync, blank, bright) are all latched on the rising edge of clk. see figure 1. figure 1: timing waveform 7,8,9 clk d ~d9 output t set t d t h t s t clk t pwh t pwl pipeline delay n-1 data n+1 note: 7. output delay (t d ) is measured from the 50% point of the rising edge of clk to the full scale transition. 8. settling time (t set ) is measured from the 50% point of full scale transition to the output remaining within 1, 2 lsb. 9. output rise/fall time (t r , t f ) is measured between the 10% and 90% points of full scale transition. digital inputs and video controls all ten bits of data (d0-d9, d0 is the lsb) are latched into the device on the rising edge of each clock cycle. there are also three video control inputs to generate composite video outputs. they are sync, blank and bright. a logic 1 on the sync input generates the sync level. a logic 1 on the blank input generates the pedestal level. bright is the bright signal input. these inputs are pipelined to maintain synchronization with the digital input data. these video controls produce the output levels needed to be compatible with video system standards. table i shows the video control effects on the analog output. note: 10. double-terminated load of 75 w . vref=1.235 v r set =165 w . inverse = 0. n2c = 1.
spt 5 12/30/98 spt5220 table ii - video control truth table 11 n2c inverse data (d9-d0) output (i/o) description 1 0 0000000000 black level binary 1111111111 white level 1 1 0000000000 white level inverse binary 1111111111 black level 0 0 1000000000 black level two's complement 0111111111 white level 0 1 1000000000 white level inverse two's complement 0111111111 black level there are two different input data formats available: binary and twos complement. in addition, these formats can be either normal or inverted. the video control truth table for these options are given in table ii. note: 11. doubly-terminated load of 75 w , sync=blank=bright=low figure 2 - typical interface circuit (external reference) reference the spt5220 can be used with either an internal or external voltage reference. the typical interface circuits are shown in figures 2 and 3. when using an external reference (figure 2), the input voltage supplied must be 1.235 volt (typ). when using the internal reference (figure 3), the v ref pin should not drive any external circuitry except for the decoupling capacitor. a bypass capacitor of 0.1 m f with the shortest possible lead lengths should be connected between v ref and v ss . with either configuration, the comp pin (compen- sation capacitor) should be connected to v dd through the bypass capacitor. the comp capacitor should be kept as close as possible to the device to keep the lead lengths to an absolute minimum. rset is the full scale adjust control. a resistor (rset) con- nected between this pin and ground controls the magnitude of the full-scale video signal. the value for rset is determined by the relationship: rset=4.1 x v ref /i out . the electrical specifications are given with an rset value of 165 ohms. component description c1, c2 10 m f capacitor c3 - c6 0.1 m f ceramic capacitor l1, l2, l3 ferrite bead r1 75 w 1% metal film resistor r2 1 k w 5% resistor r set 165 w 1% film resistor (180 w //2 k w ) z 1 1.235 v voltage reference (icl8069ccsq2) v bb dv dd c1 l1 sync blank bright d0 ~ d9 (lsb) (msb) n2c inverse clk l2 dv ss c3 c2 c4 c5 r set r1 c6 to video connector v ss v dd av dd av ss v ref i out comp r set spt5220 r2 z 1 + + l3 driving logic dv dd
spt 6 12/30/98 spt5220 component description c1, c2 10 m f capacitor c3 - c6 0.1 m f ceramic capacitor l1, l2, l3 ferrite bead r1 75 w 1% metal film resistor r set 165 w 1% film resistor (180 w //2 k w ) figure 3 - typical interface circuit (internal reference) analog output the spt5220 generates rs-343a compatible video outputs capable of directly driving a doubly-terminated 75 ohm load, and rs-170 compatible video outputs capable of directly figure 4 - composite video output wave form 14 10 ire 100 ire 7.5 ire 40 ire level ma v bright white 30.00 28.10 1.125 1.054 black 9.05 0.340 blank 7.62 0.286 sync 0.00 0.00 note: 14. doubly-terminated load of 75 w , v ref =1.235 v, r set =165 w . rs-343 levels and tolerances are assumed on all levels. note 12: av dd , dv dd and v rb must be supplied from the same source (analog +5 v) to prevent a latch-up condition due to power supply sequencing. note 13: for applications requiring minimal signal distortion, use of the external reference is recommended. l3 driving logic dv dd v bb dv dd c1 l1 sync blank bright d0 ~ d9 (lsb) (msb) n2c inverse clk l2 dv ss c3 c2 c4 c5 r set r1 c6 v ss to video connector v dd av dd av ss v ref i out comp r set spt5220 + + driving a singly-terminated 75 ohm load without the need for external buffers. figure 4 shows the video waveforms asso- ciated with the output driving the doubly-terminated 75 ohm load.
spt 7 12/30/98 spt5220 pc board considerations layout considerations to minimize noise on the power lines and ground lines, shield and decouple the digital inputs. keep the trace length be- tween groups of v dd (av dd , dv dd ) and v ss (av ss , dv ss ) as short as possible to minimize inductive ringing. supply and ground considerations use a 0.1 m f ceramic capacitor in parallel with a 10 m f tantalum capacitor for decoupling between the power line and the ground line. the digital power plane (dv dd ) and the analog power plane (av dd ) are connected through a ferrite bead. the digital ground plane (dv ss ) and the analog ground plane (av ss ) are also connected through a ferrite bead. (see figures 3 and 4). locate these ferrite beads within three inches of the spt5220. digital signal interconnect the pcb line between the ttl driver (that drives the spt5220) and the input to the spt5220 will have a low impedance source and be terminated with a high impedance. it behaves like a low impedance transmission line so signal transitions will be reflected from the high impedance input of the spt5220. to reduce ringing caused by transmission line mismatch, shorten the line length or terminate the line. both serial and parallel termination methods will work, but serial is preferred. serial termination is achieved by installing a resistor of approximately 50 w between the ttl driver output and the spt5220 digital input. analog signal interconnect to minimize noise pickup and reflections due to impedance mismatch, locate the spt5220 as closely as possible to the output connector. the line between the dac output and the monitor input should be regarded as a transmission line since it can cause problems in transmission line mismatch. use the double-termination method to avoid these problems. by using the double terminated method, the transmission lines are matched, providing an ideal, nonreflective system. inches millimeters symbol min max min max a 0.198 typ 5.08 typ b 0.117 0.140 3.00 3.60 c 0.014 0.022 0.36 0.56 d 0.099 typ 2.54 typ e 0.055 0.063 1.42 1.62 f 0.008 0.014 0.20 0.35 g 0.142 0.158 3.65 4.05 h 0.000 0.594 15.24 i 0.523 0.538 13.40 13.80 j 1.439 1.455 36.90 37.30 k 0 .080 typ 2.04 typ l0 15 a b c d e 1 28 j k f g h i l 28-lead plastic dip (pdip) package outline
spt 8 12/30/98 spt5220 pin assignments ordering information part number temperature range package type SPT5220SCN 0 to +70 c 28l plastic dip pin functions name function av dd analog power n/c no connection v bb substrate power (connected to av dd ) av ss analog ground d9 - d0 digital inputs (d9=msb, d0=lsb) sync sync signal input (logic 1 generates level) blank blank signal input (logic 1 generates level) bright bright signal input dv dd digital power dv ss digital ground clk clock input (ttl-compatible) inverse inverse signal input i out analog current output n2c two's complement signal input (active low) v ref voltage reference (externally driven) r set full-scale adjust control comp compensation capacitor comp r set v ref n2c i out av ss inverse clk dv ss dv dd bright blank sync d (lsb) av dd n/c v bb av dd av ss (msb) d9 d8 d7 d6 d5 d4 d3 d2 d1 1 28 2 3 4 5 6 7 8 27 26 25 24 23 22 21 20 19 18 17 16 15 9 10 11 12 13 14 pdip signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited . warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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